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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 67
PIC16F62X
12.0 UNIVERSAL SYNCHRONOUS/
ASYNCHRONOUS RECEIVER/
TRANSMITTER (USART)
MODULE
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI). The USART can be
configured as a full duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be config-
ured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/
A integrated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to
be set in order to configure pins RB2/TX/CK and RB1/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
REGISTER 12-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1
= Master mode (Clock generated internally from BRG)
0
= Slave mode (Clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1
= Selects 9-bit transmission
0
= Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1
= Transmit enabled
0
= Transmit disabled
bit 4
SYNC: USART Mode Select bit
1
= Synchronous mode
0
= Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode
1
= High speed
0
= Low speed
Synchronous mode
Unused in this mode
bit 1
TRMT: Transmit Shift Register STATUS bit
1
= TSR empty
0
= TSR full
bit 0
TX9D: 9th bit of transmit data. Can be PARITY bit.
Note
1: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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